Wednesday, 2018-05-30

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openstackgerritLi Liu proposed openstack/cyborg master: Added cyborg fpga programming spec  https://review.openstack.org/55939502:11
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shaohe_fengzhipengh[m], I have update the wiki  https://wiki.openstack.org/wiki/Cyborg#How_to_contribute07:59
shaohe_fengadd DevStack Quick Start link to the wiki07:59
shaohe_fengso New contributors can follow it setup their cyborg env.08:00
shaohe_fengAny issue during the setup, they can fix it and feedback to community.08:01
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openstackgerritMerged openstack/cyborg master: doc fix: devstack setup doc can not display well  https://review.openstack.org/57096809:24
openstackgerritwangzhh proposed openstack/cyborg master: Load cyborg-api app with paste_deploy  https://review.openstack.org/57093109:25
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openstackgerritwangzhh proposed openstack/cyborg master: Load cyborg-api app with paste_deploy  https://review.openstack.org/57093109:39
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Sundar#info Sundar14:03
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sum12no meeting today ?14:09
Li_Liustill waiting for Howard14:10
Li_Liushaohe_feng can you start the meeting for us?14:10
Li_Liuin case Howard is in middle of something\14:10
SundarThe meeting topic is set to 'spec review day'. Was that announced earlier?14:11
Li_LiuI think that is for a few week earlier14:12
shaohe_fengLi_Liu, hello14:14
Li_Liulet start the meeting shaohe_feng14:15
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shaohe_feng #startmeeting openstack-cyborg14:15
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shaohe_feng#topic Roll Call14:16
Sundar#info Sundar14:16
shaohe_feng#info shaohe_feng14:16
Li_Liu#info Li_Liu14:16
Li_Liu#topic summit summary14:17
Li_Liuam I doing it right?14:17
Li_Liuchanging the topic14:17
shaohe_fengyes.14:18
shaohe_fengwelcome Li_Liu introduce his experience during summit.14:18
Li_Liuok, a few of us went to the summit last week. Welcome to Canada for those of you who came14:18
Li_LiuWe had a few talks given regarding to Cyborg14:19
Li_LiuI gave a Cyborg project update. Friends from Lenovo gave a demo using Cyborg to manage GPUs in their ThinkCloud product14:20
Li_LiuJF. Ding also gave a talk with 99 cloud folks, which involves cyborg a lot14:20
Li_Liuthe general feedback is great. A lot of attentions are coming the way to Cyborg14:21
shaohe_fenggood.14:21
Li_Liucouple quick comments from the audiences14:22
sum12any recurring comments ?14:22
Li_Liu1. Managing GPUs is still not a killer app for Cyborg. Prob showing other capabilities on top of this might draw more attentions14:23
Li_Liu2. In order to become a strong piece of OpenStack or even addition to k8s in the future, we need to push the development further and faster14:25
Li_Liuas we are actually facing competitions from the Nova vGPU management.14:25
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Li_Liucurrently we are at pretty much the same stage as them.14:26
Li_Liusome people are looking at us since they think currently vGPU management in Nova should just be temperate.14:27
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Li_LiuThey believe once Cyborg becomes more mature, it should be the one actually solve the general problem14:28
Li_LiuThis is from me.14:28
Li_Liuanyone else has anything to share?14:28
SundarI moderated a session on Cyborg/FPGA in Cloud/NFV.14:29
shaohe_fengSundar, can you give a summary about it?14:29
SundarIt was meant for discussion with operators and end users. We had Verizon, SKA and CERN there, apart from many developers, incl. Nova developers14:30
SundarThe discusison is here: #link https://etherpad.openstack.org/p/Cyborg-FPGA-Support-for-Cloud-NFV14:30
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SundarOne of the main conclusions is that the model where VM issues programming requests (what we called run-time programming) is important14:31
SundarHowever, we do not have a good end-to-end flow for that today.14:31
SundarThis is an open question that we should address.14:31
Li_LiuThe main concern is who to trigger the programming right?14:32
SundarThat is one of the main concerns, the other being the validity of the bitstream itself14:32
Li_Liuah, that one14:33
SundarFor example, if a developer is developing new RTL inside the VM, the resulting bitstream may have bugs. Can that compromise the shell logic? Can it result in local hot spots or other power issues that affect the FPGA chip itself?14:34
SundarI was hoping to get feedback from operators on how they plan to validate bitstreams. Has Huawei considered that question?14:35
Li_Liuin terms of operation, shall we 1. let this rtl be synthesis in a wel controlled environment. 2. Let this bitstream load on a clean room enviroment first14:35
Li_Liuactually, internally, we did have some discussion14:36
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Li_Liufor now, we might not care too much about it as most of the IPs are in house developed14:36
Li_Liubut in the case of letting 3rd party do the development14:37
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Li_LiuI think at lease  1. let this rtl be synthesis in a well controlled environment. is needed14:37
SundarIf the environment is well-controlled, the bitstream may still have bugs. So, it is necessary but not sufficient.14:38
SundarRe. "Let this bitstream load on a clean room enviroment first", that is a good idea. So, do we confine bitstream development to bare-metal instances, so that a tenant can affect only himself or the local FPGA?14:40
Li_Liuyes, that's why the 2nd point is also needed14:40
Li_Liuit depends, it might just be a VM with a entire bitstream. The cloud provider should provide a CI/CD framework for such dev work14:41
Li_Liuentire FPGA sorry :(14:41
SundarSure. By clean room environment, do you mean bare-metal instances for development?14:42
shaohe_fengLi_Liu, do you means is a VM just own a region, it does not be allowed to do program except it own the whole FPGA?14:44
Li_Liuhmm, IMO developer/user might not even care/sense this. All they care is I submit my rtl and it passed all the sanity test14:44
Li_Liushaohe_feng we are not there yet14:45
Li_Liuafter the sanity test, the synthesized bitstream is allowed to be loaded on the PR/FPGA14:46
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SundarWhat is the sanity test? Checking for power issues depends on workloads and dynamic conditions14:47
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Li_LiuSundar, as least the sanity test should check the rlt for security concerns14:50
shaohe_fengSundar, Li_Liu, the scenario, a tenant by a VM from cloud provider, he want this VM as his development evn, which means he will do his RTL iterative development in this VM14:50
Li_Liuto identify any malicious behavior14:50
shaohe_fengso there will be error during his development.14:52
Li_Liushaohe_feng, I agree.14:53
Li_LiuCloud might also want to provide Synthesis as a Service/Sanity Test as a Service14:54
Li_Liuthis we all the bitstream that are being loaded on the FPGA are gated by these services14:55
shaohe_fengyes.14:56
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Li_LiuI am not sure if Synthesis as a Service/Sanity Test as a Service will be in the Cyborg Scope. But I think all the cloud operator should definitely consider them14:59
shaohe_fengSundar, what's your opinion?14:59
SundarYes, cloud operators need to do 'something'. That often runs into conflict with two things: (a) bitstream developers often want confidentiality, (b) it is tough to take a bitstream (or even a post-fit netlist) and check whether it is 'good'15:01
SundarI suspect there is no silver bullet, and the answer will be some combination of technology and business practices15:01
SundarAnyways, the other big question was: how does the VM initiate programming?15:02
Li_LiuI agree, point b is rather complicated.15:03
shaohe_fengSundar, does the user need to push his image to glance, let cyborg do the program or he do the program in his local VM?15:04
Li_Liucurrently, our in house implementation is using REST calls15:04
Li_Liuto call the reprogramming service api15:04
SundarOne way is to let the VM have access to programming the FPGA directly. Another way is to have the VM generate the request and let it come to Cyborg. There are 2 ways to do that, both with pros and cons.15:04
SundarShaohe: both models are possible. The main question is, is the developer/tenant ok with sharing his bitstreams with the cloud provider? If so, we can upload it to Glance first15:05
Li_Liuyes, we can provide both capabilities depends on senario15:05
Li_Liuuse the 1st way when user owns the BM and entire FPGA15:06
Li_Liuuse 2nd way elsewhere15:06
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SundarLi_Liu: Sure. One way is for the VM to invoke Cyborg REST API and target the region assigned to it. Another way is for the VM to have a connection to host e.g. virtio-serial. That way, the bitstream from the VM is not going through many network paths before coming back to the host15:07
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Li_LiuWe did consider the virtio-serial way15:08
SundarIt also requires less knowledge on the VM's part: it only sends the bitstream ID or the bitstream itself, and Cyborg will target the region assigned to the VM. The VM need not know which region is assigned to it15:08
SundarLi_Liu: Cool. What is your evaluation of virtio-serial?15:08
Li_Liubut the problem is in order to control the access on who can program the FPGA, the host still need to contact Cyborg anyways15:08
SundarWell, the Cyborg agent on the host can listen to virtio-serial15:09
Li_Liuso the flow becomes virtio-serial --> Host --> Rest Call --> Cyborg --> access check --> Host --> Program15:09
SundarMay be it is multi-threaded, or has helper daemons, for scalability15:09
SundarWe don;t need REST API in this 2nd flow. The request via virtio-serial is acted upon by the Cyborg agent15:10
Li_Liuit does not save too much network access but make the flow rather complecated15:10
Li_LiuBut the Agent needs to download the bitstream from glance15:10
SundarAre you assuming that REST API is involved, even with virtio-serial? If not, it is a simple 1-hop without TCP/IP networking15:11
Li_Liuand glance needs to check if this user can use this specific bitstream15:11
Li_LiuI think is real use case, you can not avoid REST calls15:11
Li_LiuThis is a cloud environment after all15:11
SundarLi_Liu: true. Either the VM provides the bitstream, which is validated for authenticity/encryption in some way. Or, the VM request refers to a bitstream id in glance15:12
SundarLi_Liu: "you can not avoid REST calls" Why is that? For checking whether the tenant has privileges?15:13
Li_LiuOne of the methodologies is not to allow use send a bitstream to load directly15:14
Li_Liuthis is case, the bitstreams are either coming from Glance, or from a synthesis server15:15
Li_Liuwe don't want to allow the use send a unkown bitstream through virtio-serial and blindly A15:16
Li_Liuload it to the FPGA15:16
SundarOops, running late for my next meeting. Good discussion. :) I'll check back here as much as I can.15:17
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Li_Liuactully, I gotta run as well... I am still on vacation...15:17
Li_Liushaohe_feng, could you terminate the meeting and log the conversation, we can pick it up later15:18
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shaohe_fengOK. we can discuss more about it next time.15:20
shaohe_feng#topic docs15:21
shaohe_fengwe need to improve cyborg docs.15:21
shaohe_feng I have update the wiki  https://wiki.openstack.org/wiki/Cyborg#How_to_contribute15:21
shaohe_fengadd DevStack Quick Start link to the wiki15:21
shaohe_fengso New contributors can follow it setup their cyborg env.15:21
shaohe_feng Any issue during the setup, they can fix it and feedback to community.15:22
Li_LiuI will try to work on it with couple other folks in doc tesam15:22
shaohe_fengLi_Liu, good, thanks.15:22
shaohe_fengAoB?15:22
shaohe_fengOK, let's end the meeting.15:23
shaohe_feng#endmeeting15:23
shaohe_feng#endmeeting15:24
shaohe_fengbye.15:24
sum12i think start meeting was not considered as there was space before startmeeting :)15:26
Li_Liulol15:27
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shaohe_feng#endmeeting15:45
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shaohe_feng_#endmeeting15:46
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openstackgerritSundar Nadathur proposed openstack/cyborg master: Specification for Cyborg/Nova interaction for scheduling.  https://review.openstack.org/55471722:04
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