15:03:03 <zhipeng> #startmeeting openstack-cyborg
15:03:04 <openstack> Meeting started Wed Jan 17 15:03:03 2018 UTC and is due to finish in 60 minutes.  The chair is zhipeng. Information about MeetBot at http://wiki.debian.org/MeetBot.
15:03:06 <openstack> Useful Commands: #action #agreed #help #info #idea #link #topic #startvote.
15:03:08 <openstack> The meeting name has been set to 'openstack_cyborg'
15:03:26 <zhipeng> NokMikeR to welcome you back to the team lol
15:03:32 <zhipeng> #topic Roll Call
15:03:34 <NokMikeR> :)
15:03:40 <NokMikeR> #info Mike Rooke, Nokia.
15:03:48 <zhipeng> #Howard
15:03:51 <zhipeng> shit
15:03:57 <zhipeng> #info Howard
15:04:10 <jkilpatr> #info Justin
15:04:13 <NokMikeR> dont worry you can fix that in post production.
15:04:17 <jkilpatr> good morning everyone.
15:04:51 <zhipeng> morning, evening, half-day struggling everyone
15:05:53 <NokMikeR> morning / evening all. Im back, not that I was actualy away, just busy trying to get something installed.
15:06:39 <zhipeng> NokMikeR always great to have you
15:06:46 <Vipparthy> Good Morning Folks
15:06:47 <zhuli> #info zhuli
15:08:05 <zhuli> morning/evening everyone
15:09:13 <zhipeng> #topic Queens Dev Progress
15:09:18 <zhipeng> #link https://review.openstack.org/#/q/status:open+project:openstack/cyborg
15:09:38 <Li_Liu> #info Li_Liu
15:09:40 <zhipeng> glad we finally managed to land lots of patches last week
15:09:51 <zhipeng> let's comb through the ones we have
15:10:04 <zhipeng> #info FPGA data modeling
15:10:20 <zhipeng> #link https://review.openstack.org/526559
15:10:27 <Li_Liu> I have just submitted a patch for zhuli's comments
15:10:39 <zhipeng> zhuli have you reviewed the updated patch ?
15:11:05 <zhuli> reviewing now
15:11:53 <zhipeng> other than zhuli's comment, any other concerns about this spec ?
15:15:03 <zhipeng> if there are no other concerns, we should land this spec today
15:15:12 <zhipeng> #action landing fpga data modeling spec today
15:15:27 <zhipeng> #info zhuli's api/db patch
15:15:43 <zhipeng> #link https://review.openstack.org/527396
15:16:12 <zhipeng> jkilpatr crushil could either of you guys give a workflow +1 for this patch ?
15:16:21 <zhipeng> crushil_
15:17:43 <jkilpatr> I'm still confused, the tox command should run linters but not actual test code.
15:17:59 <jkilpatr> unless the tox.ini is setup to run actual test code in the linter categories which I don't think it is
15:18:04 <zhuli> liliu, you mean the attributes are constant which will be initialized with deployable object together and do not need further methods to modify?
15:21:59 <zhipeng> Li_Liu per zhuli's question ?
15:22:14 <zhipeng> zhuli could you take a look at jkilpatr's problem ?
15:22:54 <Li_Liu> Zhuli, yes, that's what I meant
15:24:00 <Li_Liu> the attributes table should be transparent to users
15:25:24 <zhuli> jkilpatr, tox can support both linters check and unit test according to your command, for instance 'tox -epep8' for linters and 'tox -epy27' for unittest
15:27:53 <zhuli> the openstack-tox-pep8 and openstack-tox-py27 gerrit jobs run against these two situation
15:28:47 <jkilpatr> ok there we go I'll wf it
15:29:04 <jkilpatr> unless crushil_ has objections?
15:31:06 <zhuli> jkilpatr, you can see the detail in these links
15:31:07 <zhuli> http://logs.openstack.org/96/527396/11/check/openstack-tox-pep8/185864a/job-output.txt.gz#_2018-01-13_18_12_47_975849
15:31:18 <zhuli> http://logs.openstack.org/96/527396/11/check/openstack-tox-py27/7cf69da/job-output.txt.gz#_2018-01-13_18_08_40_533805
15:34:37 <zhipeng_> #info crushil_'s generic driver
15:34:41 <zhipeng_> #link https://review.openstack.org/525057
15:34:45 <zhipeng_> crushil_ any ETA on a full implementation ready for review and landing ?
15:34:48 <zhuli> liliu, ok, I'm ok with this, will help merge the patch if there is no other objections
15:35:10 <Li_Liu> Thanks a lot Zhuli
15:35:36 <crushil_> zhipeng_, It's almost ready. Need to write accompanying unit tests
15:35:55 <crushil_> You can start reviewing now
15:35:59 <zhipeng_> sounds gr8t !
15:36:15 <zhipeng_> #action land zhuli's pacth today
15:36:31 <zhipeng_> #action start reviewing crushil_'s generic driver patch
15:37:03 <zhipeng_> i think what we miss now is the conductor's report functionality to sync up resource info with Placement
15:37:14 <zhipeng_> jkilpatr could you help on this ?
15:37:30 <zhipeng_> on the basis of zhuli's patch
15:37:54 <Vipparthy> Also Zhipeng, Any feedback on Cyborg-Nova Integration Code
15:38:15 <jkilpatr> zhipeng_, this is on crushil_'s patch?
15:38:30 <jkilpatr> or zhuli's patch?
15:38:51 <zhipeng_> zhuli's
15:39:17 <jkilpatr> I'll look at it
15:39:31 <zhipeng_> something like adding a report.py from nova-compute to cyborg-conductor
15:39:42 <zhipeng_> with the corresponding modifications
15:40:45 <zhipeng_> #action jkilpatr to start working on the cyborg-conductor report function
15:41:13 <zhipeng_> Vipparthy the above mentioned code is about the cyborg-nova integration
15:41:27 <zhipeng_> Dutch dude are you still around ?
15:43:58 <zhipeng_> $topic Xilinx SDAccel introduction
15:44:07 <zhipeng_> #topic Xilinx SDAccel introduction
15:45:29 <zhipeng> #topic Xilinx SDAccel introduction
15:45:50 <zhipeng> So I'm glad to have Dutch from Xilinx to join our dev team
15:45:58 <zhipeng> Dutch the floor is yours sir
15:46:30 <zhuli> dutch welcome
15:47:20 <Dutch> Thanks! Hey everyone, I work with the Xilinx SDAccel team on our cloud program. I can help provide any resources or support from Xilinx. Also can help with SDAccel framework in general
15:48:10 <Dutch> We are still coming up to speed on the Cyborg project but the project looks great and we are happy to get involved
15:49:54 <zhipeng> Dutch could you provide some info on SDAccel ?
15:50:37 <Dutch> Sure, SDAccel is basically the framework for PCIe attached Xilinx FPGAs. Currently we use two PFs. PF0 is user space for DMA and PF1 is management for ioctls
15:52:02 <Dutch> Are people familiar with the driver at all?
15:52:17 <zhipeng> I think you could give a quick overview :P
15:52:52 <Dutch> Haha, I can't say I have done it over IRC before, this is usually consumed in slides with lots of images
15:53:39 <Dutch> Also, caution, I am not on the drivers team, so there are times when I don't know all the details
15:53:42 <zhipeng> haha i know
15:53:55 <zhipeng> maybe you could drop a link here ?
15:54:01 <zhipeng> for a good overview slide ?
15:54:29 <Dutch> Sure #link https://www.xilinx.com/html_docs/xilinx2017_4/sdaccel_doc/index.html
15:54:37 <zhuli> thanks, that's very helpful
15:55:20 <Dutch> These are most of the user guides in one place instead of dealing with the PDFs, contents are the same
15:55:21 <zhipeng> gr8t thx!
15:55:40 <zhipeng> are there any support yet in the OpenStack for SDAccel ?
15:55:46 <zhipeng> for example nova driver ?
15:56:41 <Dutch> There is also a helpful platform guide UG1164, this is still a PDF
15:56:47 <Dutch> #link https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1164-sdaccel-platform-development.pdf
15:57:11 <NokMikeR> are there any xilinx parts with an open bitstream? (and tools to program them)?
15:57:33 <Dutch> Still no nova support, our openstack cluster is using pass-through, which as you can image is a serious limitation
15:59:08 <Dutch> The drivers could be open, but bitstream generation is IP so unlikely we will ever see that open
16:00:00 <Dutch> NokMikeR, what in particular do you want open?
16:00:40 <NokMikeR> any way to program the device via e.g an arm cpu so the synthesis and routing is done on the board - that way the entry level for the programmer is lower.
16:03:13 <Dutch> For drivers and runtime, absolutely. For synthesis and P&R, I am less sure.
16:04:01 <Dutch> I am also not sure what "done on the board" means
16:04:59 <NokMikeR> pcie board with fpga + additional cpu to generate the bitstream. you send that vhdl/verilog, "other code" and it all magically works :)
16:05:34 <NokMikeR> self contained basically. no reliance on vivado etc.
16:06:10 <NokMikeR> anyhow we are offtopic here, so Howard please carry on :)
16:06:26 <zhipeng> no this is actually an interesting topic :P
16:06:27 <Dutch> It is nice to think about but yeah, I would say that is a ways off
16:07:25 <zhipeng> NokMikeR I know there are open source bitstream FPGA cards, but not sure if it is production level
16:07:46 <Dutch> It might be possible to run Vivado on the add-in-card but as far as Vivado being open that seems very unlikely
16:08:03 <Dutch> I would push the currently open project to do something like this
16:08:25 <zhipeng> Dutch so coming back to SDAccel, the software defined here refering to ?
16:09:25 <Dutch> SDAccell was initially built to support OpenCL memory model, and there is also support for OpenCL kernel code
16:09:49 <Dutch> but it has advanced some to support iteration of HLS C and RTL IP
16:10:21 <zhipeng> got it
16:10:38 <Dutch> It was designed to be flexible so that it would support future models, MPI for example
16:11:10 <zhipeng> folks thx very much for the gr8t discussion today, i'm afraid I have to close the meeting now
16:11:45 <zhipeng> please go help reviewing the patch or drafting one, we have two weeks left before Queens code freeze
16:12:05 <zhipeng> so let's squeeze in as many stuff as we could :)
16:12:33 <NokMikeR> was the devstack bug report about the permissions for cyborg solved?
16:13:14 <zhipeng> yes NokMikeR
16:13:22 <NokMikeR> Great :)
16:14:09 <zhipeng> okey meeting adjourned
16:14:13 <zhipeng> #endmeeting